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VYUHA
Ravikumar C., Sastry S. Integration, the VLSI Journal11 (2):141-157,1991.Type:Article
Date Reviewed: Aug 1 1992

The maze router presented here allows both Manhattan wires and diagonal wires. The “mixed-slope routing” model proposed by the authors is of more theoretical interest than practical use. The problems arise when the 45° and 135° lines are superimposed on the routing grid formed by horizontal and vertical lines. If the orthogonal lines are separated by minimum spacing, the diagonal lines will be too close to satisfy the design rules. The authors realize the problem of vias at non-grid points, but neglect the spacing rules between adjacent diagonal wires. In order to make the model valid, the grid size must be the worst-case design rule spacing. When the grid size equals &sqrt;2 times the minimum spacing, however, not only will the routing area be doubled, but the pin spacing will need to be enlarged as well.

Leaving aside these practical issues, the authors present their ideas well. Some interesting and illustrative examples of channel routing and switchbox routing are shown, where pins are located on the boundary. The authors do not mention whether pins can be located inside the routing region, although conceivably this case can be handled by a maze router. The comparison of wire length in Burstein difficult channel is misleading, because the unit length of a diagonal wire is not equal to the unit length of an orthogonal wire. The formation of acute angles when a wire changes its direction is often undesirable due to its poor electrical property. Finally, I am skeptical about the use of parallel processing for maze routing, due to its nature of routing one net at a time.

Reviewer:  Howard Chen Review #: CR115605
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Placement And Routing (B.7.2 ... )
 
 
VLSI (Very Large Scale Integration) (B.7.1 ... )
 
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