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  Browse All Reviews > Hardware (B) > Integrated Circuits (B.7) > Design Aids (B.7.2) > Placement And Routing (B.7.2...)  
 
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  1-10 of 55 Reviews about "Placement And Routing (B.7.2...)": Date Reviewed
  MaizeRouter: engineering an effective global router
Moffitt M.  ASP-DAC 2008 (Proceedings of the 2008 Asia and South Pacific Design Automation Conference, Seoul, Korea,  Jan 21-24, 2008) 226-231, 2008. Type: Proceedings

Routing is an essential step in the process of modern very large-scale integration (VLSI) physical design. Without an effective and efficient router, it is difficult to implement the physical layout of an integrated circuit that may contain millio...

Apr 17 2009
  The coming of age of (academic) global routing
Moffitt M., Roy J., Markov I.  Physical design (Proceedings of the 2008 International Symposium on Physical Design, Portland, Oregon,  Apr 13-16, 2008) 148-155, 2008. Type: Proceedings

Very-large-scale integration (VLSI) combines thousands of transistor-based systems on a single chip. This paper is a concise and elegant repository of the current state of the art of VLSI global routing. The paper provides background information o...

Jun 12 2008
  Chip placement in a reticle for multiple-project wafer fabrication
Wu M., Lin R., Tsai S.  ACM Transactions on Design Automation of Electronic Systems 13(1): 1-21, 2008. Type: Article

The fabrication costs of integrated circuits (IC) are extremely high. Multiproject wafers (MPW) are used to integrate, onto microelectronics wafers, a number of different IC designs from various teams, including designs from private firms, stude...

May 14 2008
  Hierarchical partitioning of VLSI floorplans by staircases
Majumder S., Sur-Kolay S., Bhattacharya B., Das S.  ACM Transactions on Design Automation of Electronic Systems 12(1): 7-es, 2007. Type: Article

The partitioning of floorplans is an important topic in the field of very large-scale integration (VLSI) physical design automation. Proper partitioning of floorplans can lead to not only efficient insertion of repeaters, but also efficient global...

Feb 6 2008
  A novel net-degree distribution model and its application to floorplanning benchmark generation
Wan T., Chrzanowska-Jeske M.  Integration, the VLSI Journal 40(4): 420-433, 2007. Type: Article

This paper provides an accurate estimate of interconnect net-degree distribution for multiterminal nets (referred to as a weighted exponential model), and for generating larger floorplanning benchmarks. The proposed technique is an interesting way...

Sep 26 2007
  Modeling wire delay, area, power, and performance in a simulation infrastructure
Carter N., Hussain A.  IBM Journal of Research and Development 50(2): 311-319, 2006. Type: Article

The Liberty simulation infrastructure models chip area, wire length, and power consumption. This paper presents an interesting modeling system, Justice, that is a set of extensions to Liberty....

Nov 29 2006
  An algorithm for integrated pin assignment and buffer planning
Xiang H., Tang X., Wong M.  ACM Transactions on Design Automation of Electronic Systems 10(3): 561-572, 2005. Type: Article

With a drastic reduction in minimum feature sizes, interconnects are dominating deep sub-micron very large-scale integration (VLSI) physical design. As such, several techniques have evolved to reduce the interconnect delay. One effective and often...

Nov 30 2005
  Automatic cell placement for quantum-dot cellular automata
Ravichandran R., Lim S., Niemier M.  Integration, the VLSI Journal 38(3): 541-548, 2005. Type: Article

Ravichandran, Lim, and Niemier develop the first cell-level placement of quantum-dot cellular automata (QCA) circuits to help automate the design process. QCA placement proceeds in three steps: zone partitioning, zone placement, and cell placement...

Aug 17 2005
  Interconnect-power dissipation in a microprocessor
Magen N., Kolodny A., Weiser U., Shamir N.  System level interconnect prediction (Proceedings of the 2004 international workshop, Paris, France,  Feb 14-15, 2004) 7-13, 2004. Type: Proceedings

This paper discusses the important issue of power dissipation in the design of high-performance microprocessors. Its major focus is on dynamic power consumption due to the switching of capacitors, and on the role of the interconnect power in this....

May 7 2004
  Printed circuit board designer’s reference
Robertson C.,  Prentice Hall PTR, Upper Saddle River, NJ, 2003.Type: Book (9780130674814)

Introductory information about printed circuit board (PCB) designs is presented in this book. It is organized into eight chapters. The first chapter introduces basic terminology, along with some structural details of a PCB. Some limitations and co...

Mar 12 2004
 
 
 
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