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	Integration, the VLSI Journal Elsevier Science Publishers B. V.         Options: Date Reviewed Title Author Publisher Published Date Descending Order Ascending Order     1-10 of 44 reviews Date Reviewed     Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms Singh K., Jain A., Mittal A., Yadav V., Singh A., Jain A., Gupta M. Integration, the VLSI Journal 60 25-38, 2018.  Type: Article This paper proposes a methodology for optimizing and evaluating chip designs by coupling the well-known logical effort (LE) theory with heuristic algorithms. Complementary metal–oxide–semiconductor (CMOS)-level optimization can dramati... Mar 1 2018   Effective usage of redundancy to aid neutralization of hardware Trojans in integrated circuits Gunti N., Lingasubramanian K. Integration, the VLSI Journal 59 233-242, 2017.  Type: Article Hardware Trojans (HTs) are a major concern in cyber-physical systems security. Outsourcing activities related to the design and implementation of digital systems expose them to malicious modification. Such modifications may long stay s... Nov 22 2017   Frame buffer-less stream processor for accurate real-time interest point detection Licciardo G., Boesch T., Pau D., Di Benedetto L. Integration, the VLSI Journal 54(C): 10-23, 2016.  Type: Article In the big data era, pictures are used as key information points in various applications such as ecommerce, entertainment, social networking, and medical diagnostics. Images contain huge amounts of information, and processing an image ... Nov 16 2016   Design of two low-power full adder cells using GDI structure and hybrid CMOS logic style Foroutan V., Taheri M., Navi K., Mazreah A. Integration, the VLSI Journal 47(1): 48-61, 2014.  Type: Article Adders are the fundamental building blocks of arithmetic and logic units, and any small improvements in adders can be translated into significant improvements for overall computing. Therefore, it is currently an active research topic. ... Mar 24 2015   Secure and resilient software: requirements, test cases, and testing methods Merkow M., Raghavan L., CRC Press, Inc., Boca Raton, FL, 2012. 278 pp.  Type: Book (978-1-439866-21-4) Nobel laureate James D. Watson exhorts you to “read around your subject” [1]; for what it’s worth, so do I. Despite my experience as a specialist in safety-critical software, I nevertheless read, enjoyed, ... May 3 2013   A novel net-degree distribution model and its application to floorplanning benchmark generation Wan T., Chrzanowska-Jeske M. Integration, the VLSI Journal 40(4): 420-433, 2007.  Type: Article This paper provides an accurate estimate of interconnect net-degree distribution for multiterminal nets (referred to as a weighted exponential model), and for generating larger floorplanning benchmarks. The proposed technique is an int... Sep 26 2007   Novel state minimization and state assignment in finite state machine design for low-power portable devices Shiue W. Integration, the VLSI Journal 38(4): 549-570, 2005.  Type: Article The goal of the paper is to develop synthesis techniques for the next-state logic in finite state machines (FSMs) to optimize power, area, and delay. While technically sound, numerous grammatical, typographical, and figure errors cloud... Feb 17 2006   Automatic cell placement for quantum-dot cellular automata Ravichandran R., Lim S., Niemier M. Integration, the VLSI Journal 38(3): 541-548, 2005.  Type: Article Ravichandran, Lim, and Niemier develop the first cell-level placement of quantum-dot cellular automata (QCA) circuits to help automate the design process. QCA placement proceeds in three steps: zone partitioning, zone placement, and ce... Aug 17 2005    New approach to design for reusability of arithmetic cores in systems-on-chip Margala M., Wang H. Integration, the VLSI Journal 38(2): 185-203, 2004.  Type: Article This paper represents an important practical contribution to the field of microelectronic hardware design. Its stated purpose is to present a novel set of practices and procedures for designing multifunctional, reusable modules for use... Aug 17 2005   Methods for evaluating and covering the design space during early design development Gries M. Integration, the VLSI Journal 38(2): 131-183, 2004.  Type: Article Design space exploration (DSE) is the process of examining alternate implementations of a system at different points in the ranges of performance, cost, memory usage, power usage, time to market, and other metrics.... Jun 15 2005       Display 510152550100 per column
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