The generation of tests for sequential circuits is of practical interest because manufacturing imperfections mean that not all manufactured circuits will be defect-free. It is desirable to have a set of tests that can uncover the maximum possible number of faults for the minimal test size.

This paper describes a two-phase system for generating tests that satisfy both of these criteria. Both phases use genetic algorithms to find the tests. In each phase, the tests are run against a hybrid fault simulator to evaluate the test, and decide which tests will be used to create the next generation. In the second phase, the winning tests from the first phase are extended to improve coverage. In this phase, rather than using random pattern sequences to generate the extensions, a deterministic test generation algorithm is used to seed the gene pool for extensions. The paper includes a table comparing the results of this method with results obtained by other methods.