Search w/in this Title for Titles All Reviews
	Journal of Electronic Testing: Theory and Applications Kluwer Academic Publishers         Options: Date Reviewed Title Author Publisher Published Date Descending Order Ascending Order     1-10 of 13 reviews Date Reviewed     Verilog HDL simulator technology: a survey Tan T., Rosdi B. Journal of Electronic Testing: Theory and Applications 30(3): 255-269, 2014.  Type: Article, Reviews: (2 of 2) The design of modern integrated circuits has become so complex that it is no longer possible to imagine a tool flow that doesn’t start from a specification in a higher-level hardware description language (HDL). Among the avai... Jun 30 2015   Verilog HDL simulator technology: a survey Tan T., Rosdi B. Journal of Electronic Testing: Theory and Applications 30(3): 255-269, 2014.  Type: Article, Reviews: (1 of 2) Tan et al. discuss the origin of Verilog, as well as its standardization and widespread adoption as one of the most popular hardware description languages (HDLs) for synthesis and behavioral modeling. The paper is well written and easy... May 27 2015   Construction and analysis of augmented time compactors Gizdarski E. Journal of Electronic Testing: Theory and Applications 27(2): 109-122, 2011.  Type: Article Test response compaction has been an active field of study in the semiconductor industry for decades. This paper is a recent addition to the research. Gizdarski extends Mazumder’s intrinsically 2D notion of the augmented prod... Nov 29 2011   MDSI: signal integrity interconnect fault modeling and testing for SoCs Chun S., Kim Y., Kang S. Journal of Electronic Testing: Theory and Applications 23(4): 357-362, 2007.  Type: Article The authors of this work are trying to develop a more accurate and powerful model to help improve the signal integrity fault coverage of long on-chip data-bus type interconnects of modern system-on-a-chip (SoC) devices. Experiments and... Mar 20 2008   Evaluating different solutions to design fault tolerant systems with SRAM-based FPGAs Sterpone L., Sonza Reorda M., Violante M., Kastensmidt F., Carro L. Journal of Electronic Testing: Theory and Applications 23(1): 47-54, 2007.  Type: Article Since a significant percentage of the static random access memory (SRAM) in a field-programmable gate array (FPGA) is devoted to configuring the logic blocks and routing interconnecting wires, single event upsets (SEUs) produced by cos... Jul 26 2007   Implementing symmetric functions with hierarchical modules for stuck-at and path-delay fault testability Rahaman H., Das D., Bhattacharya B. Journal of Electronic Testing: Theory and Applications 22(2): 125-142, 2006.  Type: Article Using an elegant recursive array structure, the authors obtain very large-scale integration (VLSI) circuit implementations of any symmetric function of n variables that are robustly path delay fault testable. A robus... Mar 28 2007   Concurrent error detection in a polynomial basis multiplier over GF(2m) Lee C., Chiou C., Lin J. Journal of Electronic Testing: Theory and Applications 22(2): 143-150, 2006.  Type: Article Using time redundancy, the authors of this paper guarantee detection of any single-cell functional fault in a semisystolic (one global feedback line in each row of the array) clocked array implementation of the title multiplier. By pip... Jan 25 2007   ADOFs and resistive-ADOFs in SRAM address decoders: test conditions and March solutions Dilillo L., Girard P., Pravossoudovitch S., Virazel A., Borri S., Hage-Hassan M. Journal of Electronic Testing: Theory and Applications 22(3): 287-296, 2006.  Type: Article The title of this paper says it all. The paper examines address decoder open faults (ADOFs) and resistive-ADOFs (not quite open, but where an unexpected resistance is present). Circuit simulations determine conditions that are sufficie... Dec 13 2006   Concurrent error detection in a bit-parallel systolic multiplier for dual basis of GF(2m) Lee C., Chiou C., Lin J. Journal of Electronic Testing: Theory and Applications 21(5): 539-549, 2005.  Type: Article Efficient finite field arithmetic is important in a number of applications, including error correcting and cryptography. The most time-consuming finite field operation is multiplication, and, for this reason, it has received a consider... Jun 12 2006   Mutation analysis and constraint-based criteria: results from an empirical evaluation in the context of software testing Soares I., Vergilio S. Journal of Electronic Testing: Theory and Applications 20(4): 439-445, 2004.  Type: Article We are sometimes able to show that one testing criterion is stronger than another in some sense: for example, branch coverage (namely, covering all the edges in a program graph) includes statement coverage (which just ensures all nodes... Nov 10 2005       Display 510152550100 per column
	Reproduction in whole or in part without permission is prohibited.   Copyright 1999-2024 ThinkLoud® Terms of Use | Privacy Policy