Adders are the fundamental building blocks of arithmetic and logic units, and any small improvements in adders can be translated into significant improvements for overall computing. Therefore, it is currently an active research topic. This paper focuses on improving the design of adders, mainly regarding power minimization and secondarily noise immunity. The researchers propose two new symmetric designs for full adder cells using a gate-diffusion input (GDI) structure and hybrid complementary metal-oxide semiconductor (CMOS), which is a combination of CMOS and complementary pass transistor logic (CPL) styles.

Comparative results in terms of a 0.13 micrometers (μm) and 90 nanometers (nm) process technology for differing voltages have been obtained for these adders along with four other adders: complementary CMOS (C-CMOS), CPL, another hybrid full adder from Goel et al. [1], and an ultralow-power full adder (ULPFA) [2].

The results clarify how the proposed adder performed better in terms of both delay and power minimization while providing full voltage swing. However, all these adders belong to the group of ripple carry adders (RCAs) that are known to be slow compared to carry-lookahead and tree adders. Therefore, without full comparison with other classes of adders, it is not very clear to readers whether these adders could be immediately applicable for practical purposes.