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A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures
Fidalgo A., Alves G., Gericota M., Martins Ferreira J.  Integrated circuits and system design (Proceedings of the Twenty-first Annual Symposium on Integrated Circuits and System Design, Gramado, Brazil, Sep 1-4, 2008)22-27.2008.Type:Proceedings
Date Reviewed: Nov 5 2008

For maximum benefit, users of fault-tolerant (FT) systems must be assured that all components are fault free at the beginning of a mission. This is a very difficult task since, by design, faults are masked and tolerated.

Fidalgo et al. demonstrate that the controllability and observability features provided by on-chip debug (OCD) infrastructures can be easily enhanced to inject single-bit flip faults--simulating single-event upset (SEU) faults--into fault-tolerant systems to validate the reliability of the hardware at any instant in time. The paper contains a comparative analysis of various fault-injection methods, including offline and real-time methods using basic OCD structures, extended OCD structures, and customer-designed fault-injection modules. Experiments are performed on both standard and FT systems. The results suggest that designers of systems with OCD capabilities should consider adding fault-injection capacity, especially if the design involves FT features.

This paper is well written, technically sound, and readable by nonexperts.

Reviewer:  F. Gail Gray Review #: CR136213 (1004-0377)
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Reliability, Testing, And Fault-Tolerance (B.8.1 )
 
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