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  Browse All Reviews > Hardware (B) > Performance And Reliability (B.8) > Reliability, Testing, And Fault-Tolerance (B.8.1)  
 
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  1-10 of 38 Reviews about "Reliability, Testing, And Fault-Tolerance (B.8.1)": Date Reviewed
  Tolerating transient illegal turn faults in NoCs
Huang L., Zhang X., Ebrahimi M., Li G. Microprocessors & Microsystems 43(C): 104-115, 2016.  Type: Article

Faults in on-chip level networks are very common. There have been multiple approaches to detect and correct faults in different levels, such as the error-detecting code (EDC) and error-correcting code (ECC) used in the data packet, cyc...

Jul 29 2016
  Execution trace-driven energy-reliability optimization for multimedia MPSoCs
Das A., Singh A., Kumar A. ACM Transactions on Reconfigurable Technology and Systems 8(3): 1-19, 2015.  Type: Article

Dynamic task scheduling and fault tolerance in multiprocessor systems-on-chip (MPSoCs) are explored in this paper. The paper describes a heterogeneous MPSoC system with a special fault-free node called RTM to manage the other processin...

Aug 19 2015
  Automated synthesis of resilient and tamper-evident analog circuits without a single point of failure
Kim K., Wong A., Lipson H. Genetic Programming and Evolvable Machines 11(1): 35-59, 2010.  Type: Article

When talking about fault tolerance, we seek to put in place mechanisms that would keep a system running with minimal degradation, despite the malfunctioning of a component. Typically, in the case of failure, redundant components jump i...

Aug 19 2010
  GRID codes: strip-based erasure codes with high fault tolerance for storage systems
Li M., Shu J., Zheng W. ACM Transactions on Storage 4(4): 1-22, 2009.  Type: Article

As the authors correctly suggest in the introduction, no code is perfect and selecting code for an application always involves tradeoffs. Although GRID codes--“a new family of erasure codes with high fault tolerance&...

May 26 2010
  Selective replication: a lightweight technique for soft errors
Vera X., Abella J., Carretero J., González A. ACM Transactions on Computer Systems 27(4): 1-30, 2009.  Type: Article

By selectively replicating only those instructions that have the highest probability of failing due to soft errors--caused by particle strikes, noise, electromagnetic interference, or electrostatic discharge--Vera et ...

Mar 11 2010
  Automatic test generation for combinational threshold logic networks
Gupta P., Zhang R., Jha N. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16(8): 1035-1045, 2008.  Type: Article

Two nanoscale devices that implement threshold logic are resonant tunneling diodes (RTDs) and quantum cellular automata (QCA). A threshold logic gate (TLG) computes the sign of the weighted sum of its inputs, compared with a threshold....

Jun 12 2009
  SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects
Xu Q., Zhang Y., Chakrabarty K. ACM Transactions on Design Automation of Electronic Systems 14(1): 1-27, 2009.  Type: Article

This paper addresses the problem of reducing the time spent on testing core-to-core interconnections, namely on the verification of signal-integrity faults, typically relevant in high-performance systems on chip (SOC). The review of th...

Jun 4 2009
  Exploiting selective placement for low-cost memory protection
Mehrara M., Austin T. ACM Transactions on Architecture and Code Optimization 5(3): 1-24, 2008.  Type: Article

This paper introduces a new, promising way of protecting embedded memory by exploring architecture alternatives--partial protection--and compiler optimizations--program profiling and selective placement of co...

Mar 5 2009
  StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems
Gupta S., Feng S., Ansari A., Blome J., Mahlke S.  CASES 2008 (Proceedings of the 2008 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, Atlanta, GA, Oct 19-24, 2008) 1-10, 2008.  Type: Proceedings

The paper begins with a reliability analysis to justify the selection of pipeline stages as the granularity level for redundant elements. StageNetSlice (SNS) is a complete pipeline design, modified to allow reconfiguration. The CMP sys...

Feb 26 2009
  A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures
Fidalgo A., Alves G., Gericota M., Martins Ferreira J.  Integrated circuits and system design (Proceedings of the Twenty-first Annual Symposium on Integrated Circuits and System Design, Gramado, Brazil, Sep 1-4, 2008) 22-27, 2008.  Type: Proceedings

For maximum benefit, users of fault-tolerant (FT) systems must be assured that all components are fault free at the beginning of a mission. This is a very difficult task since, by design, faults are masked and tolerated....

Nov 5 2008
 
 
 
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