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1 - 10 of 54
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Behavior-level observability analysis for operation gating in low-power behavioral synthesis
Cong J., Liu B., Majumdar R., Zhang Z. ACM Transactions on Design Automation of Electronic Systems 16(1): 1-29, 2010. Type: Article
As the authors demonstrate in this paper, observability analysis at the behavioral level, before operations are scheduled, can lead to significant reductions in power consumption. This is done by gating clocks on the output registers o...
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Mar 2 2011 |
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Using the minimum set of input combinations to minimize the area of local routing networks in logic clusters containing logically equivalent I/Os in FPGAs
Ye A. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18(1): 95-107, 2010. Type: Article
This is a very good academic paper, but it contains little of practical value to most design teams. It shows that the area of local routing networks that connect cluster inputs to individual lookup table (LUT) inputs can be significant...
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Feb 8 2011 |
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Semi-automatic derivation of timing models for WCET analysis
Schlickling M., Pister M. ACM SIGPLAN Notices 45(4): 67-76, 2010. Type: Article
Schlickling and Pister propose, in this paper, a method for deriving timing models using the information in formal very-high-speed integrated circuit (VHSIC) hardware description language (VHDL) specifications, in a semi-automatic way....
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Sep 20 2010 |
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GRID codes: strip-based erasure codes with high fault tolerance for storage systems
Li M., Shu J., Zheng W. ACM Transactions on Storage 4(4): 1-22, 2009. Type: Article
As the authors correctly suggest in the introduction, no code is perfect and selecting code for an application always involves tradeoffs. Although GRID codes--“a new family of erasure codes with high fault tolerance&...
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May 26 2010 |
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Selective replication: a lightweight technique for soft errors
Vera X., Abella J., Carretero J., González A. ACM Transactions on Computer Systems 27(4): 1-30, 2009. Type: Article
By selectively replicating only those instructions that have the highest probability of failing due to soft errors--caused by particle strikes, noise, electromagnetic interference, or electrostatic discharge--Vera et ...
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Mar 11 2010 |
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StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems
Gupta S., Feng S., Ansari A., Blome J., Mahlke S. CASES 2008 (Proceedings of the 2008 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, Atlanta, GA, Oct 19-24, 2008) 1-10, 2008. Type: Proceedings
The paper begins with a reliability analysis to justify the selection of pipeline stages as the granularity level for redundant elements. StageNetSlice (SNS) is a complete pipeline design, modified to allow reconfiguration. The CMP sys...
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Feb 26 2009 |
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A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures
Fidalgo A., Alves G., Gericota M., Martins Ferreira J. Integrated circuits and system design (Proceedings of the Twenty-first Annual Symposium on Integrated Circuits and System Design, Gramado, Brazil, Sep 1-4, 2008) 22-27, 2008. Type: Proceedings
For maximum benefit, users of fault-tolerant (FT) systems must be assured that all components are fault free at the beginning of a mission. This is a very difficult task since, by design, faults are masked and tolerated....
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Nov 5 2008 |
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The research of self-repairing digital circuit based on embryonic cellular array
Zhang Z., Wang Y., Yang S., Yao R., Cui J. Neural Computing and Applications 17(2): 145-151, 2008. Type: Article
Following a well-known column-elimination strategy, this paper satisfies the stated goal of successfully implementing a self-repairing mechanism using lookup tables (LUT). Successful repair is validated by a simulation of a faulty cell...
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Jun 25 2008 |
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A methodology for transistor-efficient supergate design
Kagaris D., Haniotakis T. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15(4): 488-492, 2007. Type: Article
Though well written, this paper addresses a very limited audience: those designing custom chips, in which chip area is the crucial parameter....
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Feb 27 2008 |
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Self-orthogonal 3-(56,12,65) designs and extremal doubly-even self-dual codes of length 56
Harada M. Designs, Codes and Cryptography 38(1): 5-16, 2006. Type: Article
If you want to know that the code generated by the rows of a block-point incidence matrix of a self-orthogonal 3-(56,12,65) design is a doubly-even self-dual code of length 56, that the code words of minimum weight generate an extremal...
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Jan 15 2008 |
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