Anyone interested in very large-scale integration (VLSI) circuit design, the effects of manufacturing process parameter variations, failure mechanisms in VLSI chips, fault modeling of chip failures, testing VLSI chips, design for test (DFT) techniques, or simply in learning how to write a good technical paper should read this paper.

It begins by analyzing failures due to process variations in high-density circuits, such as static random access memory. After modeling these failures as logical faults, the authors show that two likely types of logical faults, deceptive read destructive faults (DRDF) and low supply data retention faults (LSDRF), are not covered by basic March test sequences (complexity 10N, where N is the number of memory addresses). After developing an extended March sequence (complexity 12N) that covers both DRDF and LSDRF faults, the authors propose a DFT technique called double sensing that allows the extended March sequence to be shortened back to complexity 10N. The cost of the DFT circuit is a 2.7 percent reduction in memory access time and a 1.15 percent increase in chip area. As a bonus, the authors show how the DFT circuit can also be used during normal circuit operation to improve the quality of any online error detection or error correction functions that might be used to prevent random read errors.

Almost everyone will find something new in this excellent paper. Since memory subsystems tend to dominate state-of-the-art microprocessor-based systems, the techniques described in this paper are prime candidates for application in system-on-a-chip designs.