Critical area estimation is very important for estimation of yield in very large scale integration (VLSI). Traditional approaches for estimating the critical area usually considered only the diameter of a circular model for the real defects. To avoid large errors in estimating the critical area, the authors propose a theoretical framework that considers using the directional extension of defects, in place of diameter only.

The authors present several figures that make the proposed model based on the directional extension much more understandable. In their experimental results section, they demonstrate the accuracy of the proposed approach, as compared to traditional approaches. The stochastic simulation results provide a certain understanding of the robustness of the process, which will be important when the approach is used in practical situations, as parameter variations will become prominent.

Readers would do well to think about the examples in Figure 6. It will be clear why there is little difference in the results between the proposed PWLI model and the average circle model, considering the linearity of function expressed by Formula 22.

The paper is presented theoretically. It would be appropriate for readers who are conducting research on yield estimation in VLSI. Although there are a lot of mathematical formulas in this paper, which might discourage readers in other areas, the step-by-step derivations are very clear if readers follow them patiently, with the assistance of background knowledge in probabilistic methods.