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Area-time optimal VLSI integer multiplier with minimum computation time
Mehlhorn K., Preparata F. Information and Control58 (1-3):137-156,1984.Type:Article
Date Reviewed: Jun 1 1985

Before introducing research results, the authors present a complete and well described survey of the major results of the integer multiplication problem from the point of view of the direct VLSI circuit realization. Then they define a class of optimal VLSI multipliers of n bit integers, where the optimality is studied according to the AT2 VLSI measure of complexity. Execution time for the new multipliers varies in the range of [(logn), 0(:.PC9 :3- Wz:Ln)], while previously defined VLSI circuits, for the same problem, required time in the range [&OHgr;(log2n),0(:.PC9 √Ln)].

The results presented in this paper are relevant, especially from a theoretical point of view. In fact, the problem of VLSI integer multiplication is settled because it is shown that there exists an AT2 optimal VLSI multiplier for the entire spectrum of computation time.

Reviewer:  L. Pagli Review #: CR108776
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VLSI (Very Large Scale Integration) (B.7.1 ... )
 
 
Algorithms Implemented In Hardware (B.7.1 ... )
 
 
Computations On Discrete Structures (F.2.2 ... )
 
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