This work is different. It is not about logic design or the design of integrated circuits. It is neither a theoretical treatment, a classroom text, nor a case study guide. It covers the difficulties of implementing a logic design at the system level with due consideration of electrical and mechanical environments. Buchanan combines enough theory to understand the problems of high-speed system implementation with helpful hints, guidance, and design tips to mitigate problems associated with high-speed systems.
The material is covered in 15 chapters of about 15 pages each. Chapter 1 introduces the electrical and mechanical issues the designer is faced with and stresses the need for due consideration of worst-case device and interconnection timing delays, electromagnetic principles, and Ohm’s law in realizing a board- or system-level design. Chapter 2 covers advanced CMOS and BiCMOS logic families, concentrating on the interpretation of external specifications for the 54/74 series. Chapter 3 discusses internal characteristics from the perspective of the limitations of devices, such as latch-up and its prevention, electrostatic discharge, and static and dynamic power dissipation. The remaining chapters cover specific design issues and problems and offer a list of helpful hints in the form of dos and don’ts. Their titles describe them adequately: (4) Beware of Inductance and Transient Switching Currents; (5) Power Distribution; (6)Signal Interconnections; (7) Transmission Line Effects; (8)Clock Distribution; (9) Device, Board, Unit Interfaces; (10)Noise Tolerant Logic Architectures; (11) Worst Case Timing; (12) System Initialization and Low-Voltage Sensing; (13)Memory Subsystem Design; (14) Using PLDs, FIFOs, and Other LSI Devices; and (15) ASIC Application Tips.
The useful tips provided in each chapter range from some that are relatively obvious to those that are not. Examples include
Take into account the slowing effect of distributed loads on line propagation delay. As a very rough rule of thumb, allow an additional 0.15 ns per load (“Worst Case Timing”)
Clocked devices with TTL input levels should be selected so that all devices clock on the low-to-high clock transition to maximize the noise margin (“Noise Tolerant Logic Architectures”)
Pull up reset signals where they enter units, boards, etc., so that reset will not be asserted when the normal source is not present (“System Initialization”)
The typical change in propagation delay versus load capacitance is 15 ps/pF for most advanced BiCMOS and CMOS devices.
The book includes three appendices. “Conversion Factors” should have been either eliminated or expanded to contain useful information like wire length time equivalents. “Definition of Symbols and Acronyms” is useful, while “Trademarks” may be obligatory, but is of little use. At 12 pages, the index is complete. The references provided are adequate (about 20 per chapter) and mostly recent. No exercises are included, since this volume is more a guidebook for practitioners than a text for students.
I recommend this book highly as a reference for anyone implementing medium- to high-speed board- or system-level logic systems using CMOS or BiCMOS logic devices. The section on memory subsystem design is somewhat disappointing, since the organizing principles it covers are relatively primitive considering the state of current designs. These principles are applicable to almost any design regardless of its organization, however.
The biggest problem with the book is the possibility that the reader will take all of the advice and hints literally. Clearly, much of the information consists of rough approximations. The author makes clear throughout that the intent is to improve the understanding of the factors that must be considered and to provide guidance that must be carefully assessed and not blindly applied. I commend him for the clarity of his presentation, which includes ample warnings. He has produced a useful addition to the practicing engineer’s toolkit.
