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Reviews about "Design Styles (B.3.2)":
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Evaluating the combined effect of memory capacity and concurrency for many-core chip design
Liu Y., Sun X. ACM Transactions on Modeling and Performance Evaluation of Computing Systems 2(2): 1-25, 2017. Type: Article
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Cache vulnerability mitigation using an adaptive cache coherence protocol
Maghsoudloo M., Zarandi H. The Journal of Supercomputing 68(3): 1048-1067, 2014. Type: Article
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Towards virtual shared memory for non-cache-coherent multicore systems
Ramesh B., Ribbens C., Varadarajan S. IPDPSW 2013 (Proceedings of the 2013 IEEE 27th International Symposium on Parallel and Distributed Processing Workshops,May 20-24, 2013) 1186-1193, 2013. Type: Proceedings
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Hybrid nonvolatile disk cache for energy-efficient and high-performance systems
Shi L., Li J., Jason Xue C., Zhou X. ACM Transactions on Design Automation of Electronic Systems 18(1): 1-23, 2012. Type: Article
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An efficient cache strategy for improving images’ quality
Cheng H., Wu T., Lee W. ICIMCS 2009 (Proceedings of the 1st International Conference on Internet Multimedia Computing and Service, Kunming, Yunnan, China, Nov 23-25, 2009) 49-52, 2009. Type: Proceedings
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Efficient memory management for hardware accelerated Java Virtual Machines
Bertels P., Heirman W., D’Hollander E., Stroobandt D. ACM Transactions on Design Automation of Electronic Systems 14(4): 1-18, 2009. Type: Article
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 Utilizing shared data in chip multiprocessors with the Nahalal architecture
Guz Z., Keidar I., Kolodny A., Weiser U. SPAA 2008 (Proceedings of the 20th Annual Symposium on Parallelism in Algorithms and Architectures, Munich, Germany, Jun 14-16, 2008) 1-10, 2008. Type: Proceedings
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