Field-programmable gate array (FPGA)-based reconfigurable computing has proven to be successful in the areas of biochemistry, linear algebra, and digital signal processing (DSP). Both high-performance computation units and efficient interconnections are important to the FPGA accelerator’s final performance. In the past few years, numerous high-performance intellectual property (IP) cores have been developed, for different applications. This paper proposes a runtime system that automatically configures suitable connections for IP cores, and ultimately helps to develop a friendly programming model that can automatically build up the system using existing IPs.

Compared to general-purpose central processing units (CPUs) and other types of accelerators, such as graphics processing units (GPUs) and cell processors, FPGAs require the most development effort, although they provide the finest-tuned architectures. FPGA developers need to have a solid knowledge of hardware; the lack of programming models isolates programmers from hardware details, thus preventing FPGA accelerators’ popularity. Therefore, automatically connecting existing IPs will allow FPGA accelerators to be more widely applied.

The authors briefly cover several different aspects of their project. Readers who are unfamiliar with this project may find it difficult to follow the paper. Overall, since the paper presents new ideas on FPGA synthesis for reconfigurable computing, it should interest readers who work in the field.