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1-8 of 8 Reviews about "
Automatic Synthesis (B.6.3...)
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Digital logic design using Verilog: coding and RTL synthesis
Taraate V., Springer International Publishing, New York, NY, 2016. 416 pp. Type: Book (978-8-132227-89-2)
Anyone who wants to read this book must have a sound background in the theoretical aspects of digital logic design. This book presents digital logic design using the hardware description language known as Verilog. The book starts with ...
Apr 27 2017
Slotless module-based reconfiguration of embedded FPGAs
Patterson C., Athanas P., Shelburne M., Bowen J., Surís J., Dunham T., Rice J. ACM Transactions on Embedded Computing Systems 9(1): 1-26, 2009. Type: Article
Field-programmable gate array (FPGA)-based reconfigurable computing has proven to be successful in the areas of biochemistry, linear algebra, and digital signal processing (DSP). Both high-performance computation units and efficient in...
Jan 13 2010
A methodology for transistor-efficient supergate design
Kagaris D., Haniotakis T. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15(4): 488-492, 2007. Type: Article
Though well written, this paper addresses a very limited audience: those designing custom chips, in which chip area is the crucial parameter....
Feb 27 2008
Synthesis of arithmetic circuits: FPGA, ASIC and embedded systems
Deschamps J., Bioul G., Sutter G., Wiley-Interscience, New York, NY, 2006. 576 pp. Type: Book (9780471687832)
This is perhaps the best and most thorough digital arithmetic design book in print. While it is mostly oriented toward practicing engineers, the well-engineered blend between basic theory, algorithm descriptions, and real-life implemen...
Jun 8 2006
Automated hardware synthesis from formal specification using SAT solvers
Greaves D. Rapid system prototyping (Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping, Geneva, Switzerland, Jun 28-30, 2004) 15-20, 2004. Type: Proceedings
Greaves describes how formal methods can be used to design systems and circuits. In his approach, he exploits the existence of SAT solvers to check if a system satisfies its specification or not. Systems to be checked are modeled as fi...
Apr 14 2005
A predictive distributed congestion metric and its application to technology mapping
Shelar R., Sachin ., Saxena P., Wang X. Physical design (Proceedings of the 2004 international symposium on Physical design, Phoenix, Arizona, USA, Apr 18-21, 2004) 210-217, 2004. Type: Proceedings
Congestion metrics distributed over an area, instead of looking for a single congestion parameter such as wire length, are discussed in this paper. The authors present their case well, and provide a simple metric, as well as an approac...
Jun 10 2004
Two-level logic minimization for low power
Tseng J., Jou J. ACM Transactions on Design Automation of Electronic Systems 4(1): 52-69, 1999. Type: Article
In digital circuit design, the emphasis for a long time has been onminimization of the number of gates or of the area. The powerconsumption of the chip has been important, but has not formed animportant part of the design procedure, or...
Jun 1 1999
Logic synthesis for low power VLSI designs
Iman S., Pedram M., Kluwer Academic Publishers, Norwell, MA, 1998. Type: Book (9780792380764)
Tools for the automatic synthesis of digital systems in very large scale integration (VLSI) have become commonplace and indispensable. The demand for faster and denser chips is increasing, and along with it the demand for a shortened d...
Dec 1 1998
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