Controlling power leakage is important. This paper presents an optimization approach that uses dual threshold technology, based on experiments using benchmarks. The authors used full adders factored by half adders (FA/HA) in their experiments. The experiments consisted of three phases.

The first phase used the high V(t) only, by applying the timing-driven synthesis and placement technique, described in Paragraph 2.2. This resulted in an FA/HA tree structure with the least power leakage, but with the longest critical timing path, possibly violating the timing constraint. The second phase consisted of an iterative process that gradually traded off the leakage power of the initial phase with the circuit timing to meet the timing constraint. This was followed by the fine-grained refinement phase, to attempt to obtain an optimal solution. The results of the experiment demonstrate that this is possible. Figure 5 shows how this optimization occurred over critical path changes. The results demonstrated that there was 32 to 36 percent power leakage reduction in relation to the conventional method.