Computing Reviews
Today's Issue Hot Topics Search Browse Recommended My Account Log In
Review Help
Search
Architectural support for reduced register saving/restoring in single-window register files
Huguet M., Lang T. ACM Transactions on Computer Systems9 (1):66-97,1991.Type:Article
Date Reviewed: Feb 1 1992

Large register files offered by current processors allow reductions in memory traffic, since most of the data needed by a procedure are held in the processor registers. Function calls are responsible for a significant part of the overall memory traffic through register saving and restoring (RSR). This paper proposes a new policy, called policy G, for RSR across function calls. Policy G only applies to single-window file registers.

The main basic policies for RSR are clearly presented in the paper. Classic policies are static since they do not take into account the actual use of registers during execution. To reduce the RSR traffic, most compilers support intraprocedural and interprocedural optimizations for the register allocation. The main contribution of this paper is to show how hardware may be used to reduce the RSR traffic. The extra hardware is used to monitor the register usage, and a register is only saved or restored when needed: the policy is dynamic. Moreover, the authors show that the combination of a dynamic policy and compiler optimization gives better results than either method can provide by itself.

The detailed presentation of policy G is followed by a practical implementation example. This case study, based on the RISC II processor, shows that the required support hardware is simple and that most of the operations related to RSR may be performed concurrently with normal processor tasks. The authors also address the implications for the processor cycle time. The last part of the paper is dedicated to the evaluation of the obtained RSR traffic. In this section, policy G is compared to numerous policies and shows good results.

This long paper is both clear and complete. Reading it is advisable for people involved in computer architecture and processor design.

Reviewer:  G. Saucier Review #: CR115560
Bookmark and Share
 
Optimization (B.5.2 ... )
 
 
Data-Path Design (B.5.1 ... )
 
 
Languages And Compilers (B.1.4 ... )
 
 
VLSI (Very Large Scale Integration) (B.7.1 ... )
 
 
Design (B.5.1 )
 
 
Microprogram Design Aids (B.1.4 )
 
  more  
Would you recommend this review?
yes
no
Other reviews under "Optimization": Date
Fast design exploration for performance, power and accuracy tradeoffs in FPGA-based accelerators
Ulusel O., Nepal K., Bahar R., Reda S. ACM Transactions on Reconfigurable Technology and Systems 7(1): 1-22, 2014. Type: Article
Jun 3 2014
Design optimization for security- and safety-critical distributed real-time applications
Jiang W., Pop P., Jiang K. Microprocessors & Microsystems 52 401-415, 2017. Type: Article
Dec 13 2017

E-Mail This Printer-Friendly
Send Your Comments
Contact Us
Reproduction in whole or in part without permission is prohibited.   Copyright 1999-2024 ThinkLoud®
Terms of Use
| Privacy Policy