The goal of the Hector project is to explore a design region where the most cost-effective multiprocessor solutions are likely to lie. The authors argue that this region lies at the center of the processor power-coupling space. Thus, the Hector processor has the computing power of a typical workstation, and a hierarchical interconnection structure capable of supporting both local and global memory is chosen for cost-effectiveness. The distinguishing feature of Hector is in the hierarchical structure, which can be characterized by three design choices:
Short buses connecting small sets of processor-memory modules are used to support local communications.
Buses are connected by local rings and then a global ring to provide remote communications. Rings are used, instead of buses as in CM*, for the shorter average distances.
Ring sections are made independent so that ring sections and buses can operate concurrently.
The authors claim that, mainly due to this interconnection architecture, Hector has the following advantages: (1) cost and overall bandwidth can grow linearly with the size of the system, (2) with simple and fast backplane and short transmission lines, it can scale better with future technology and lead to higher performance, reliability, and flexibility, as well as lower cost, and (3) the cost of a memory access grows incrementally with the distance between the processor and memory location. This report on the design and development of the Hector multiprocessor covers design goals, system organization including interconnection architecture and communication protocol, and implementation considerations. It also justifies the architectural features and compares Hector with other multiprocessors.
This paper is informative and instructive for readers interested in computer architecture, although it deals with a single machine. It is aimed at a broad audience. Readers will find the justification of the architecture and the comparison with other multiprocessors particularly interesting.
