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Browse All Reviews > Computer Systems Organization (C) > Processor Architectures (C.1) > Multiple Data Stream Architectures (Multiprocessors) (C.1.2) > Interconnection Architectures (C.1.2...)
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1-10 of 44
Reviews about "Interconnection Architectures (C.1.2...)":
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Design of 4-disjoint gamma interconnection network layouts and reliability analysis of gamma interconnection networks
Rajkumar S., Goyal N. The Journal of Supercomputing 69(1): 468-491, 2014. Type: Article
Two designs of 4-disjoint gamma interconnection networks for reliable data communication in a tightly coupled, large-scale, multiprocessor system are described in this paper. These two designs provide four disjoint paths for each sourc...
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Jun 10 2015 |
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Localized Congestion Control in Advanced Switching Interconnects
Krishnan V., Mayhew D. IEEE Micro 25(1): 10-18, 2005. Type: Article
Almost all modern personal computers (PCs) use motherboards with input/output (I/O) buses based on the peripheral component interconnect (PCI), an open standard developed by Intel. One possible successor of PCI could be PCI Express.
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Sep 21 2005 |
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A Timed Verification of the IEEE 1394 Leader Election Protocol
Romijn J. Formal Methods in System Design 19(2): 165-194, 2001. Type: Article
Architecture standard IEEE 1394-1995 defines a high-performance serial multimedia bus that allows several components in a network to communicate at high speed. This architecture, which is still being refined and adapted, includes sever...
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Jul 18 2003 |
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Interconnection networks: an engineering approach
Duato J., Yalamanchili S., Lionel N., Morgan Kaufmann Publishers Inc., San Francisco, CA, 2002. 650 pp. Type: Book (9781558608528)
This book describes interconnection networks in depth. It contains many references that would help readers in beginning a study of the subject, in addition to many practical examples of their development and use. ...
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Feb 11 2003 |
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Fault-Tolerant Meshes with Small Degree
Zhang L. IEEE Transactions on Computers 51(5): 553-560, 2002. Type: Article
Arrays and meshes are two kinds of interconnection graphs used to represent parallel computer systems: nodes represent processors, and edges represent communication links between the processors. In such systems, if a processor fails, ...
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Feb 3 2003 |
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A New Adaptive Hardware Tree-Based Multicast Routing in K-Ary N-Cubes
Kumar D., Najjar W., Srimani P. IEEE Transactions on Computers 50(7): 647-659, 2001. Type: Article
The authors present a new mechanism to handle multicast routing in an n-dimensional k-ary torus, a widely used interconnection topology known as k-ary n-cubes. The paper first describes several proposed mech...
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May 8 2002 |
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Matrix Multiplication on the OTIS-Mesh Optoelectronic Computer
Wang C., Sahni S. IEEE Transactions on Computers 50(7): 635-646, 2001. Type: Article
The purpose of the work is designing efficient algorithms for fundamental linear algebra operations, such as vector-vector multiplication, vector-matrix multiplication, and matrix-matrix multiplication on the OTIS-Mesh optoelectronic c...
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May 3 2002 |
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Communication in the two-way listen-in vertex-disjoint paths mode
Böckenhauer H. Theoretical Computer Science 264(1): 65-90, 2001. Type: Article
Parallel architectures are based on interconnection networks having different characteristics. One important characteristic is the complexity of fundamental communication tasks of information dissemination (broadcast, accumulation and ...
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Mar 1 2002 |
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Fault-Tolerant Adaptive and Minimal Routing in Mesh-Connected Multicomputers Using Extended Safety Levels
Wu J. IEEE Transactions on Parallel and Distributed Systems 11(2): 149-159, 2000. Type: Article
A fairly restricted problem is treated in this paper. The specific formulation is for an infinite two-dimensional mesh connection of processors, in which each processor has interconnections with its four nearest neighbors in the coordi...
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Feb 1 2001 |
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A New Network Topology with Multiple Meshes
Das D., De M., Sinha B. IEEE Transactions on Computers 48(5): 536-551, 1999. Type: Article
The authors present a hierarchical mesh architecture that has a network diameter approximately equal to the square root of the diameter of a 2-dimensional mesh with the same number of processors. The practical effect is that algorithms...
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Feb 1 2000 |
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