Using the RISC (reduced instruction set computer) design methodology as a basis for discussion, the authors investigate the underlying question of how implementation design issues affect the performance of a given architecture. To provide a framework for their discussions, the authors propose a definition for RISC designs, providing the reader with a well-defined point of reference for the work.

Following a thorough discussion comparing various RISC and CISC (complex instruction set computer) architectures, a detailed case study of a well-known RISC (Berkeley’s RISC I) and a CISC (Intel’s 432) are undertaken. Using these case studies, the authors are able to illustrate their thesis that a design should be evaluated with respect to its suitability to its intended application and by the efficiency of the given implementation.

As the authors point out, the terms reduced and complex themselves imply a two-dimensional design continuum, addressing the orthogonal questions of profusion of instructions versus the functionality of the instructions themselves. Moreover, beyond the instruction set itself, other design issues, such as compiler optimization and register-set design, also directly influence the overall system performance.

By recognizing that computer design is a complex process of selecting individual features to create a given architecture, the authors clearly illustrate that efficiency cannot be obtained simply by the adherence to tenets of any design methodology.