The Reduced Instruction Set Computer (RISC) project seeks to exemplify the advantages to be gained by an architectural simplicity which permits rapid implementation of a fast single-chip processor. Although conventional in approach, RISC has a number of interesting features, including the use of a moving window of visible registers for parameter passing and local workspace, and a delayed-action jump instruction which simplifies pipeline implementation. The present paper describes RISC II, which differs from the RISC I machine described elsewhere [1] only in some details of implementation, including in particular the incorporation of a three-stage pipeline. The microarchitecture, timing, and control structure of this machine are described in some detail. In additions, a number of measures, including silicon area, power dissipation, and design time, are tabulated for the various parts of the design. These figures demonstrate a significant aspect of the RISC approach: the simplicity of the control section releases silicon area which is used for a large on-chip register file to support the moving window implementation. Otherwise, although the details given will be of interest to those working in machine design, the paper adds little in illumination of the RISC concept to what has been published previously.