Though well written, this paper addresses a very limited audience: those designing custom chips, in which chip area is the crucial parameter.

Kagaris and Haniotakis present an algorithm for selecting “appropriate” transistor-level implementations for complex gates, sometimes called supergates. The goal is to minimize the total number of transistors in the design. The algorithm is not optimal because the result obtained depends on the order in which product terms are added. If all possible orders were examined, the problem would be nondeterministic polynomial-time (NP) hard.

The actual algorithm uses a heuristic to decide on the order in which to add product terms. All four-variable functions were analyzed with results that match other published results. For four specific functions with more than four variables, Kagaris and Haniotakis improved the best known results from five percent to 25 percent.

The authors could have made a stronger case if they had examined more functions. Since the improvements were primarily due to exploitation of bridges, Kagaris and Haniotakis believe that their algorithm will provide better results for functions with more variables, since the opportunities for bridges increase. Delay and power consumption are not explicitly addressed. The algorithm adds one product term at a time to the design, with current step complexity of O(lt2s2), where l is the number of literals in the current product term, t is the total number of product terms, and s is the number of splines (a spline is a set of transistors connected in series).

For the level of complexity, the results seem limited.