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	Ginosar, Ran     Options: All Media Types Journals Proceedings Div Books Whole Books Other Date Reviewed Title Author Publisher Published Date Descending Ascending Date Reviewed     1 - 3 of 3 reviews       Compiler-directed power management for superscalars Haj-Yihia J., Asher Y., Rotem E., Yasin A., Ginosar R. ACM Transactions on Architecture and Code Optimization 11(4): 1-21, 2015.  Type: Article Modern processor architectures have complex, dynamic power demands that are difficult and expensive for the architecture’s power distribution network (PDN) to meet. This paper describes a compiler-based analysis that delimits...... Apr 27 2015     Timing optimization in logic with interconnect Morgenshtein A., Friedman E., Ginosar R., Kolodny A.  System level interconnect prediction (Proceedings of the Tenth International Workshop on System Level Interconnect Prediction, Newcastle, United Kingdom, Apr 5-8, 2008) 19-26, 2008.  Type: Proceedings The general timing optimization problem can be defined as reducing the delay of a logic path propagating over a distance between two points, while performing a logical function. This paper discusses the timing optimization in logic pat...... Jun 11 2008     An Efficient Implementation of Boolean Functions as Self-Timed Circuits David I., Ginosar R., Yoeli M. IEEE Transactions on Computers 41(1): 2-11, 1992.  Type: Article The design of self-timed logic (STL) is an important part of VLSI design. STL circuits assure that events will occur in a sequence, but no event needs to occur at any particular time. This paper addresses two issues of STL: the efficie...... Jun 1 1993
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