The general timing optimization problem can be defined as reducing the delay of a logic path propagating over a distance between two points, while performing a logical function. This paper discusses the timing optimization in logic paths with wires. It considers the optimal arrangement of repeater insertion along a high impedance wire between two points, in order to minimize the extra delays introduced by the insertion and to achieve good power efficiency.

The authors discuss a unified timing optimization approach that solves the general design problems by addressing three interrelated fundamental questions: What is the optimal size of the gates? What is the optimal number of gates/repeaters? Where should the gates be located along the wire?

A unified logical effort (ULE) model is used to address the question of gate sizing. The delays caused by wires and gates along a logic path are tightly coupled and cannot be treated separately. The ULE model extends the standard logical effort (LE) model by including the wire delay.

A gate-terminated sized repeater insertion (GSRI) technique is developed to address the question of the optimal number of gates. GSRI is an extension of the standard RI methodologies. The assumptions made by the RI methodologies may not be realistic. The GSRI technique is developed under realistic circuit constraints.

The logic gates as repeaters (LGR) concept is used to address the question of the location of the gates. The location of the gates along a path can be iteratively determined from the expression of the delay optimization goal.

Overall, this paper presents the techniques to address the fundamental questions of optimal sizing, number, and location of the gates. The combination of the proposed techniques provides solutions to a wide variety of design considerations on timing optimization in very-large-scale integration (VLSI) circuits.