Modern processor architectures have complex, dynamic power demands that are difficult and expensive for the architecture’s power distribution network (PDN) to meet. This paper describes a compiler-based analysis that delimits code regions having the potential to create exceptional power demands; the PDN reacts to these regions with actions that compensate for exceptional demand. System simulations show that delimited regions help the PDN reduce power overloads by 20 percent and overall power demand by 11 percent.

This work addresses long-term (∼10⁴ nsec) voltage drops caused by capacitor exhaustion during high current demand. These problems are met by increasing supply, which spends power, or reducing demand, causing slower execution. A modified LLVM compiler performs static analysis over control-flow graphs to identify regions likely to cause problems. Individual instructions are assigned an empirical maximum energy use normalized to the cheapest instruction. The analysis identifies and minimizes code regions with excessive power demands; the remaining code is considered safe.

A processor emulated the region-delimiting instruction and generated traces for offline simulator analysis. Tests based on SPEC CPU2006 benchmarks identified only power emergencies (no false negatives) with around 94 percent accuracy (six percent false-positive rate). The more precise false-positive rate improved average performance by around 12 percent.

This paper (section 2 in particular) requires a good grasp of central processing unit (CPU) power management. The static analysis in section 3 is basic and can be easily picked up by a reader who understands the rudiments of compiler-based analysis.