Computing Reviews
Today's Issue Hot Topics Search Browse Recommended My Account Log In
Review Help
Search
Exploiting selective placement for low-cost memory protection
Mehrara M., Austin T. ACM Transactions on Architecture and Code Optimization5 (3):1-24,2008.Type:Article
Date Reviewed: Mar 5 2009

This paper introduces a new, promising way of protecting embedded memory by exploring architecture alternatives--partial protection--and compiler optimizations--program profiling and selective placement of code and data in protected sections of memory.

The new memory architecture and placement algorithms are proven to increase memory robustness with low hardware and power costs.

Deeper research on developing more efficient compiler algorithms for program profiling and selective placement, to improve performance of the overall flow, should be conducted. This would help expedite the industrial adoption and application of the proposed new memory protection scheme.

Reviewer:  Xiaojun Li Review #: CR136562 (0910-0924)
Bookmark and Share
 
Reliability, Testing, And Fault-Tolerance (B.8.1 )
 
Would you recommend this review?
yes
no
Other reviews under "Reliability, Testing, And Fault-Tolerance": Date
Scheduling tests for VLSI systems under power constraints
Chou R., Saluja K. (ed), Agrawal V. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 5(2): 175-185, 1997. Type: Article
Feb 1 1998
Introduction to IDDQ testing
Chakravarty S., Thadikaran P., Kluwer Academic Publishers, Norwell, MA, 1997. Type: Book (9780792399452)
Feb 1 1998
Fault-tolerant self-organizing map implemented by wafer-scale integration
Yasunaga M., Hachiya I., Moki K., Kim J. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 6(2): 257-265, 1998. Type: Article
Oct 1 1998
more...

E-Mail This Printer-Friendly
Send Your Comments
Contact Us
Reproduction in whole or in part without permission is prohibited.   Copyright 1999-2024 ThinkLoud®
Terms of Use
| Privacy Policy