Turega discusses the back propagation model (BPM) for neural net simulation and presents an architectural proposal for the simulator. The proposed architecture is a hybrid based on a conventional monoprocessor (CMP) running BPM and supported by a collection of distributed processor nodes (DPNs); the DPN architecture uses a synchronous ring communication mechanism, and each DPN has its own memory.

The architecture includes a special INSTR register, which traces a current instruction for each DPN processor cycle. Data and instructions are separated via the register INPUT per machine cycle.

The standard BPM requires a special algorithm for node weight adjustment for learning procedures (this is a general problem for adaptive networks regarding dynamic interactions of models and data within the models). The adjustment time is usually exponential, and the corresponding learning algorithms are generally of exponential complexity.

The author states that a neural network simulator based on the architecture described in the note has linear performance with respect to the number of DPNs, with no scaling overheads and no stored program control; thus, the architecture admits unlimited expansion without exponential degradation of unit performance.

The paper includes no formal proofs, but the architecture is fully described. Evaluation results for the architecture are provided. This interesting paper is useful for those interested in general neural network simulation within large-model back propagation.