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An architecture for packet-striping protocols
Hari A., Varghese G., Parulkar G. ACM Transactions on Computer Systems17 (4):249-287,1999.Type:Article
Date Reviewed: Feb 1 2000

With the ever-growing power of computer CPUs (such as the recent advent of 1.0 GHz PC processors), network speeds for Internet access and Internet service provider (ISP) backbones usually become the bottlenecks. Although many new technologies, such as DSL, cable modems, Gigabit Ethernet, and WDM fiber, will certainly offer great promise in the future, some of the old gimmicks, such as data striping or reverse multiplexing, which increase communication throughput by “striping” data across multiple network links, can still work their charm.

This paper presents a new set of data-striping (packet-striping or channel-striping) algorithms that efficiently  handle  issues of variable-packet-size and first-in-first-out (FIFO) delivery with packet losses and dynamically varying skews. The most interesting feature of the proposed algorithms is that a theoretical connection (“transformation theorem”) is first established between the well-studied fair-queueing algorithms and the data-striping algorithms of load sharing, and new data striping algorithms surplus round robin (SRR) and generalized round robin (GRR) are then derived as the results of transformation from existing fair-queueing algorithms.

As a demonstration, the implementation, within the NetBSD kernel, of a simple architectural framework for striping IP packets using SRR over multiple data link interfaces (“stripe” protocol) is also included. The performance measurements and simulations show improved results over available striping schemes with scalable throughput, even when striping is done over dissimilar links (ATM and Ethernet), and the protocol synchronizes quickly after packet losses.

Reviewer:  Cui-Qing Yang Review #: CR124844 (0002-0095)
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Protocol Architecture (C.2.2 ... )
 
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