In optimizing the rendering speed of polygon meshes, the authors base their calculations on the principle that the rendering engine is of infinite speed, as they use the GL library interface for referring to a rendering engine.

GL (a graphics library of Silicon Graphics Inc.) and the SGI underlying hardware have been optimized for triangles and triangle strips, and therefore may not provide the best performance for other graphics primitives such as triangle or quad meshes.

This theoretical study shows that, based on the above GL constraint and the existence of a stack for intermediate vertex storage, an algorithm can be established that will generate the appropriate sequence of vertices to render a given polygon mesh. They also establish a relation between the time to render the polygon (that is, perform the necessary calls to GL) and the stack size requirements.

A recursive algorithm is described in which the set of vertex data splits into up to three sets at each recursion level. One of them is pushed to the stack, and the algorithm applies to the two remaining sets. According to the authors, this algorithm guarantees the minimal rendering time. Although the authors cannot present an optimal algorithm, they propose an approximation that, by using the previous optimal algorithm, can work within the constraints of a limited stack size. They then propose a way to trade stack space for execution time.

The authors conclude by proposing to extend their work to more general polygons, pushing complete polygons rather than vertex data to the stack. This might be a little overextended, considering the complexity of polygons having more than three vertices, if they must be considered as a whole.

This work presents real, applicable results to hardware architects who plan to implement a geometry pipeline and have to deal with execution space/time constraints. It also provides a good base of reflection for the possible extension or evolution of existing hardware architectures. Of course, in a real implementation, one would have to balance the cost of extra memory to be sold with a hardware platform with the net benefits obtained.