The construction of a special-purpose system built from two digital signal processing (DSP) chips for computing convolutions is described. The system uses a two-level memory approach, with local 16K memories used for program storage and a 2K shared memory for data. The shared memory is dual-ported to allow 0 wait states on simultaneous access by both processors at 40 MHz. An analog interface provides access to input signals and data, and an output signal port. Detailed chip and software descriptions are given. The reported performance of the system allowed a sample rate up to 40 microseconds for the dual processor system, nearly double the rate of a single DSP system with this architecture.