HIDEL is one more language that includes all the features necessary for modeling the structure of VLSI objects. It can describe structure (in terms of components and connections) and allows description at various levels of refinement. It supports modular description, thus enabling use of libraries; alternate structure descriptions for each module; parametrization; and iterative and recursive structure modeling. The language is a derivative of Modula-2. It uses the hierarchical hypergraph with ports (HHP), a structured graph data structure.

The paper describes the language primitives with examples, presents primitive operations on HHP, and shows a scheme for using the HIDEL-HHP system for functional simulation using Occam. The paper also remarks on how the behavior of the system can be described using HIDEL and cites two example designs. Although the paper is well written and makes useful reading for every CAD-VLSI professional, I would have liked to see some discussion of why HIDEL would be superior to VHDL or CONLAN efforts.