The ITD49C402 CMOS bit-slice sequencer has four times the level of integration and about twice the performance (20 versus 12 MIPS) of its compatible cousin, the AMD 2901C. This paper describes the basic tradeoffs in performance between the cost of power consumption and the number of parts in the design; it depicts CMOS speed/power products that are almost an order of magnitude better than those of TTL-ECL bipolar. It also compares fixed instruction set (8086 and 68000) implementations to bit-slice architectures, but does not consider ASIC or RISC implementations. The author argues that a fixed instruction set implementation (68000) will be limited to a bus rate of about 1.5 MIPS, while the bit-slice approach will yield up to 20 MIPS.

The comparisons with the 2900 family appear to be reasonable, as are the comparisons with the 8086 and 68000 fixed instruction set technologies. In the former, a one-for-one compatible substitution is effected; this substitution is easiest to validate. In the case of the 8086 and 68000, older technology is being compared, which seems somewhat unfair when one considers the current 80XXX and 68XXX technology available. The performance differential cited would shrink further for comparisons of contemporary ASIC and RISC implementations.

The paper is worth reading and should be of interest to implementors of special-purpose sequencers for ALU, graphics, or controller applications, especially since the performance of the new device is discussed in some detail.