Ivan Sutherland’s Turing Award lecture is important reading for computer designers. As used in this work, a micropipeline is a powerful combination of the concepts of pipelining, asynchronous sequential logic, and transition signaling. Along with these three main concepts, micropipelines incorporate some aspects of the “programming” method of designing hardware and of using a minimal set of functional modules for control. Sutherland does a good job of presenting the ideas as an integrated design philosophy instead of as a bag of design tricks or as a design toolkit, which is often difficult for authors of hardware design papers.

Asynchronous design has been of interest to the computer engineering community since the work of Muller and others on the ILLIAC II computer. Sutherland credits Muller’s work [1] as one root of micropipelines (though his name is accidentally misspelled in the references). Another important root is the work of Molnar, Clark, and others on macromodules [2]. Macromodules exploited difference coaxial cable transmission speeds to guarantee data arrival in advance of control signals, while Sutherland employs VLSI layout geometry for the same purpose. Transition signaling is thoroughly mixed with asynchronous design in this paper and is not always properly distinguished as a concept. An example is the praise for transition signaling because it yields the ability to do proofs of functionality, whereas these proof techniques are possible in any form of asynchronous design, whether edges or pulses are used to represent events.

The most ubiquitous root, and perhaps the most important, is pipelining. Pipelined control, which is introduced first, reminds me of the control delay style of building computer control units that Hill and Peterson advocate in their 1973 text [3]. Pipelining techniques are becoming more and more important as circuit speeds crowd the speed-of-light limit. They are also being applied at lower and lower levels of design. Systolic arrays that pipeline large operations such as floating-point multiply-add fit naturally with carry-save versions of multipliers. This paper presents a coherent methodology for doing pipelined design from the bottom up, while retaining the ability to modularize functions and have them interface consistently with other functional modules.

A cautionary note on the future applications of this methodology is that asynchronous logic, once in the days of ILLIAC II and again with the macromodules, enjoyed a brief period of intense interest and then gave way to synchronous techniques in the interests of enhanced speed with available technology. I hope the happy combination of asynchronous design with transition signaling and pipelining will make asynchronous design a mainline, rather than a peripheral, design technique.