The area addressed by this chapter is that of the simulation of digital logic circuits at the functional level and, to a lesser extent, the gate level. Although principally concerned with simulation as a means of studying the behavior of circuits under the influence of specified faults, the authors begin with an extensive review of logic simulation in general. Some of this seems unnecessarily detailed; for example, the descriptions of a hardware description language and its representation and evaluation are quite lengthy, but little reference to this is made subsequently in the context of fault simulation, in particular.

The major part of the chapter consists of a detailed study of three methods of fault simulation: parallel simulation, deductive simulation, and concurrent simulation, with algorithms and examples included for each. The chapter concludes with a brief comparison of the three methods and a discussion of some outstanding problems and issues, including the design of special-purpose machines for fault simulation.

The overall treatment is somewhat pedestrian: Details are dealt with carefully, but a more synoptic view would have been welcome. Despite this, I found this to be a most helpful, clear, and thorough introduction to this topic.