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| | Wolfgang Schreiner is an associate professor at the Research Institute for Symbolic Computation (RISC) of the Johannes Kepler University Linz in Austria. His research areas are formal methods; concurrency; and parallel, distributed, and grid computing. Wolfgang Schreiner was born in 1967 in Austria. In 1994, he earned his PhD at the Johannes Kepler University Linz under the auspices of the federal president with a thesis on parallel functional programming for computer algebra. In 2001, he earned habilitation in practical computer science for his work on parallel software and algorithms for symbolic computation. From 2001 to 2004, he was the director of the degree program "Engineering for Computer-based Learning" at the Upper Austria University of Applied Sciences campus Hagenberg, where he still serves as a lecturer. Since 2004, he has been an associate professor at the RISC institute, where he served as vice-chair from 2004 to 2007. During his career, Schreiner has participated in and directed various research projects funded by the Austrian Science Foundation, the Austrian Ministry for Science and Research, and the European Union. These projects include "Distributed Supercomputing in the Grid," "MathBroker I+II: Brokering Distributed Mathematical Services," and "HPGP: High-Performance Generic Programming." He has developed various software systems such as the para-functional language compiler pD, the parallel computer algebra software Distributed Maple, and the proving assistant RISC ProofNavigator. Currently, Schreiner is participating in the doctoral program for computational mathematics at the Johannes Kepler University with a project on formally specified computer algebra software. He is also building the RISC ProgramExplorer, a software environment for program specification, exploration, and verification. --Read our Q&A with Wolfgang Schreiner here. |
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 Vitruvius+: an area-efficient RISC-V decoupled vector coprocessor for high performance computing applications
Minervini F., Palomar O., Unsal O., Reggiani E., Quiroga J., Marimon J., Rojas C., Figueras R. ACM Transactions on Architecture and Code Optimization 20(2): 1-25, 2023. Type: Article
Vector processors had their heyday in the 1980s, before classical supercomputers were mostly replaced by multiprocessors. Today, however, vector processors are experiencing a renaissance: their efficient exploitation of data-level parallelism has ...
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Aug 2 2023 |
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A general approximation method for bicriteria minimization problems
Halffmann P., Ruzika S., Thielen C., Willems D. Theoretical Computer Science 695 1-15, 2017. Type: Article
Many applications in operations research require the simultaneous optimization of multiple (typically mutually opposing) objective functions. Since the general problem is usually computationally intractable, bicriteria optimization res...
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Nov 9 2017 |
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A high performance QDWH-SVD solver using hardware accelerators
Sukkari D., Ltaief H., Keyes D. ACM Transactions on Mathematical Software 43(1): 1-25, 2016. Type: Article
To make effective use of modern computer hardware, algorithms have to be carefully designed with concurrency in mind: in particular, they need to efficiently utilize the multiple cores provided by the computer’s general-purpo...
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Oct 20 2016 |
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Strategy based semantics for mobility with time and access permissions
Ciobanu G., Koutny M., Steggles J. Formal Aspects of Computing 27(3): 525-549, 2015. Type: Article
Process algebras represent mathematical formalisms for modeling distributed systems whose behavior may be subsequently analyzed by automatic tools that investigate all possible system executions....
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Aug 12 2015 |
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Variants of Mersenne twister suitable for graphic processors
Saito M., Matsumoto M. ACM Transactions on Mathematical Software 39(2): 1-20, 2013. Type: Article
Generating sequences of pseudorandom numbers is a prerequisite for many applications, such as Monte Carlo simulations. Since such applications are often executed on parallel computers, the parallel computation of pseudorandom numbers i...
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Jun 5 2013 |
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Smart cooperative relay schemes in LTE-advanced system
Malik S., No D., Kim D., Moon S., Kim S., Hwang I., Kim B., Lee J. ICUIMC 2012 (Proceedings of the 6th International Conference on Ubiquitous Information Management and Communication, Kuala Lumpur, Malaysia, Feb 20-22, 2012) 1-7, 2012. Type: Proceedings
A core problem of wireless data communication is how to maximize coverage while minimizing the bit error rate. To address this, the 4G technology known as long term evolution-advanced (LTE-A) features a cooperative relaying scheme in w...
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Jun 18 2012 |
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Comparing and analyzing the computational complexity of FCA algorithms
Strok F., Neznanov A. SAICSIT 2010 (Proceedings of the 2010 Annual Research Conference of the South African Institute of Computer Scientists and Information Technologists, Bela Bela, South Africa, Oct 11-13, 2010) 417-420, 2010. Type: Proceedings
The development of a semantic Web with data that machines can understand depends crucially on the formal representation of knowledge in suitable ontologies (that is, sets of concepts within certain domains). The goal of formal concept ...
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Jul 22 2011 |
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Programming matrix algorithms-by-blocks for thread-level parallelism
Quintana-Ortí G., Quintana-Ortí E., Geijn R., Zee F., Chan E. ACM Transactions on Mathematical Software 36(3): 1-26, 2009. Type: Article
For the last few years, decomposing processors into multiple cores that operate independently, in parallel, within a shared address space, has increased the power of computer processors. This paper presents a new method for programming...
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Sep 2 2009 |
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