Search
An FPGA-based parallel architecture for on-line parameter estimation using the RLS identification algorithm
Ananthan T., Vaidyan M. Microprocessors & Microsystems38(5):496-508,2014.Type:Article
To:
Your Colleague's E-mail:
From:
Your E-mail:
Subject:
Reviews: An FPGA-based parallel architecture for on-line parameter estimation using the RLS identification algorithm
Message Body:
Reproduction in whole or in part without permission is prohibited. Copyright 1999-2024 ThinkLoud
®
Terms of Use
|
Privacy Policy