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An FPGA-based parallel architecture for on-line parameter estimation using the RLS identification algorithm
Ananthan T., Vaidyan M. Microprocessors & Microsystems38 (5):496-508,2014.Type:Article
Date Reviewed: May 19 2015

The focus of this paper is the optimization and implementation of a recursive least squares (RLS) algorithm for online parameter estimation in systems. The main thrust deals with optimizations to make the algorithm more amenable for implementation, followed by actual implementation on both a field-programmable gate array (FPGA) and an application-specific integrated circuit (ASIC) for comparison.

Online parameter estimation deals with the problem of identifying unknown parameters given a model of the system and actual input and output data over time. The paper deals with a particular real-world case of a servo position control system: identifying unknown parameters and then tuning the system to obtain the best performance. The key challenge is doing this in real time. This requires implementing the algorithm directly on an FPGA or ASIC for speed. Unfortunately, some of the operators in the RLS algorithm are too expensive to place in the critical path, and therefore a significant portion of the paper is taken up with optimizing it. Two optimizations appear to stand out. The first is eliminating the need for computing matrix inverses. The second deals with expressing necessary multistage matrix multiplications in a form that is amenable to pipelining. The paper evaluates the final algorithm on both an FPGA and an ASIC. The implementation significantly outperforms the state of the art thanks to these optimizations (table 8).

Overall, the paper is an interesting read in that it shows the end-to-end process of optimizing the mathematics of an algorithm to make it amenable to hardware implementation, followed by actual implementation, functional verification, and a performance evaluation. The paper, however, is very heavy on the theory and mathematics of the RLS algorithm, a necessity since it revolves around optimizing it. This could possibly be somewhat of an impediment for the interested reader without a background in the subject.

Reviewer:  Amitabha Roy Review #: CR143446 (1508-0715)
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Least Squares Methods (G.1.6 ... )
 
 
Gate Arrays (B.7.1 ... )
 
 
Microprocessors And Microcomputers (B.7.1 ... )
 
 
Parallel Architectures (C.1.4 )
 
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Moniot R. Applied Numerical Mathematics 59(1): 135-150, 2009. Type: Article
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