With systems-on-a-chip (SOC) expected to exceed the one billion transistor milestone within the next few years, the authors seek a new coding strategy to reduce power consumption. This paper addresses the saturation of transistor chip and interwire capacitance.

After a brief summary of current bus encoding techniques, highlighting the increasing importance of interwire parasitic capacitances in deep submicrometer technology, the authors describe an adaptive dictionary encoding scheme (ADES), which they claim can reduce power consumption by roughly 25 percent. This strategy adapts a bus energy minimization via transition pattern coding proposed by Sotiriadis and Chandrakasan [1]. Their experiment suggests that dictionary techniques, such as LZW compression, can reduce power encoding, by relying on the high frequencies of a small number of patterns in trace files. As such, a small dictionary can be quite effective.

The application of dictionary techniques to bus encoding has led the authors to their ADES scheme: the original data word is divided into three parts (the bypassed part (wo), index part (wi), and upper part (N-wi-wo)). Encoding and decoding algorithms and architecture are described, as is dictionary adaptation. Using only part of the data word results in energy saving.

Exclusion of the index part of the data word also increases the hit rate. Finally, degraded system performance can be reduced by pipelining the data transfer process.

In summary, energy savings in transmission overhead presumably outweighs investment in the proposed encoding/decoding strategy. One caveat: style and grammatical blemishes do not enhance this paper’s presentation.