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VLSI implementation of a stochastic database machine for relational algebra and hashing
Elleithy K., Bayoumi M., Delcambre L. Integration, the VLSI Journal11 (2):169-190,1991.Type:Article
Date Reviewed: Oct 1 1992

Better and faster database machines (DBMs) are definitely needed because of the speed at which databases grow and proliferate. This research paper describes a special-purpose database processor implemented as a VLSI systolic array. Its intended use is as a relational database backend processor for a host.

The paper’s eight sections are well balanced. After the introduction, Section 2, “Prior Work,” briefly summarizes several previously proposed DBMs. Section 3, “Motivations Beyond a New SDBM,” presents drawbacks of previous DBMs and explains how this new DBM tries to avoid them. A brief review of the relational model and relational algebra operations is presented in Section 4, “Relational Data Model.”

The authors have tried to develop a DBM that is both versatile and simple. It supports relational algebra operations (select, project, Cartesian product, union, difference, and join) for database queries, and hashing operations (member, insert, and delete) for accessing and modifying the database. The resulting one-dimensional systolic array is linear in space and time. The basic cell is simple and programmable in order to support all the operations. Operations on the array can be pipelined. Details of how the cells must be programmed, the scheduling of data at the inputs, and the collection of data from the outputs are given in Section 5, “A New SDBM,” and Section 6, “Hashing Mode.” For hashing, the authors depart from the standard systolic model by using global communications (broadcast). This raises questions concerning the expandability of the array.

A prototype of a 4-bit cell for the DBM is described in Section 7, “VLSI Implementation.” The 3&mgr; process used looks outdated today, when sub-micron technologies are common. The design is a combination of static and dynamic domino complementary metal oxide semiconductor (CMOS) and shows concern for the speed-area tradeoff generally encountered in VLSI design.

The paper is useful for researchers and design engineers in DBMs and in the broader areas of VLSI and systolic arrays. It has an appropriate review of previous work and can be a good starting point for studying or implementing DBMs.

Reviewer:  Mircea Stan Review #: CR115607
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Database Machines (H.2.6 )
 
 
Algorithms Implemented In Hardware (B.7.1 ... )
 
 
VLSI (Very Large Scale Integration) (B.7.1 ... )
 
 
VLSI Systems (C.5.4 )
 
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