The reliability of digital computer systems is affected by transient and intermittent faults. Because of the nature of these faults, systems must be tested under operational conditions in order to detect them. Unfortunately, such online monitoring often requires much additional software or redundant hardware.

This paper presents a processor monitoring approach called Signatured Instruction Streams (SIS). The SIS approach consists of small additions to the executable software and a little additional hardware.

The application program is partitioned into blocks of instructions with an accompanying signature word. When the application program is run, the signatures for each block are regenerated and compared to the stored signatures. The addition of these signatures increases the code size by only ten percent. Both the assembler and loader programs for the processor must be modified to perform this signature computation. The entire signature embedding process is transparent to the user.

Monitoring hardware is attached to the address and control lines of the processor being monitored in order to detect incorrect signatures. The basic clock rate of the processor is unaffected.

A programmable hardware fault inserter was designed to insert faults on the external data, address, and control buses of the MC68000 chip. Although the MC68000 has a reasonably effective fault detection mechanism built in, the SIS detects a much higher percentage of faults and significantly reduces the average detection latency of most fault types. Incorporation of SIS into the architecture of the MC68000 is estimated to require an additional nine percent of the silicon real estate.

This is a well-written paper. The legends for figures 13–15 are missing, but the balance of the accompanying diagrams and charts is clear and supportive.