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1 - 10 of 13
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Optimizing image processing on multi-core CPUs with Intel parallel programming technologies
Kim C., Kim J., Lee D. Multimedia Tools and Applications 68(2): 237-251, 2014. Type: Article
A comparison of the use of serial, data, and task parallelism in image processing is presented in this paper. The first part of the paper describes the convolution operations that are used for edge detection during image processing. Th...
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Jul 9 2015 |
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Parallel programming: for multicore and cluster systems
Rauber T., Rünger G., Springer Publishing Company, Incorporated, Berlin, Germany, 2013. 525 pp. Type: Book (978-3-642378-00-3)
Most of this book involves techniques and hardware structures that have been around the supercomputing community for decades. However, these old ideas are much more relevant to the whole programming community now that sequential comput...
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Jan 24 2014 |
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A compiler framework for the reduction of worst-case execution times
Falk H., Lokuciejewski P. Real-Time Systems 46(2): 251-300, 2010. Type: Article
This paper describes the worst-case execution time (WCET)-aware C compiler (WCC) for the TriCore TC1796 processor. Instead of transformations that improve the average performance of a program, this compiler only uses transformations th...
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Jun 6 2011 |
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 Stack allocation of objects in the CACAO virtual machine
Molnar P., Krall A., Brandner F. PPPJ 2009 (Proceedings of the 7th International Conference on Principles and Practice of Programming in Java, Calgary, Alberta, Canada, Aug 27-28, 2009) 153-161, 2009. Type: Proceedings
In languages such as Java, all objects are allocated on the heap, creating two types of inefficiency: costly memory allocation and slower access to the data in the object. This paper addresses the inefficiency by performing a series of...
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May 3 2010 |
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Semi-sparse flow-sensitive pointer analysis
Hardekopf B., Lin C. POPL 2009 (Proceedings of the 36th Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, Savannah, GA, Jan 21-23, 2009) 226-238, 2008. Type: Proceedings
This paper describes techniques for dramatically improving the performance of flow-sensitive, context-insensitive pointer analysis. It is a combination of improved engineering, careful data structure decisions, and new algorithm optimi...
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Jun 12 2009 |
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Control flow optimization in loops using interval analysis
Ghodrat M., Givargis T., Nicolau A. CASES 2008 (Proceedings of the 2008 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, Atlanta, GA, Oct 19-24, 2008) 157-166, 2008. Type: Proceedings
This paper presents a new transformation for improving execution in nested loops that contain an innermost single conditional statement. First, the algorithm estimates the maximum and minimum values of the variables involved in conditi...
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Apr 23 2009 |
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Conquer compiler complexity
Wu X., VDM Verlag, Saarbrücken, Germany, 2008. 172 pp. Type: Book (9783836498562)
Two parts of the problem of compiler complexity--parser modularity and associating semantics (or similar operations) with the data structures built by the parser--are addressed in this book. To improve parser modulari...
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Mar 10 2009 |
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Copy coalescing by graph recoloring
Hack S., Goos G. PLDI 2008 (Proceedings of the 2008 ACM SIGPLAN Conference on Programming Language Design and Implementation, Tucson, AZ, Jun 7-13, 2008) 227-237, 2008. Type: Proceedings
This paper is a continuation of a recent revolution in graph coloring register allocation based on the work of Chaitin and others. Chaitin’s technique has two drawbacks: repeated building of an expensive data structure called...
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Mar 5 2009 |
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Reducing register pressure in SMT processors through L2-miss-driven early register release
Sharkey J., Loew J., Ponomarev D. ACM Transactions on Architecture and Code Optimization 5(3): 1-28, 2008. Type: Article
Superscalar processors and register renaming make it easy to simulate multiple processors on a single physical processor, improving the utilization of the computing units. When a memory reference to a location that is no...
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Feb 27 2009 |
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Lazy instruction scheduling: keeping performance, reducing power
Mahjur A., Taghizadeh M., Jahangir A. Low power electronics and design (Proceeding of the Thirteenth International Symposium on Low Power Electronics and Design, Bangalore, India, Aug 11-13, 2008) 375-380, 2008. Type: Proceedings
The problem of “useless instruction execution” is addressed in this paper. An instruction is useless if the result is never used. With reasonable compilers, this problem can only take place when conditional branches...
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Nov 20 2008 |
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