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1 - 6 of 6
reviews
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 An FPGA-based VLIW processor with custom hardware execution
Jones A., Hoare R., Kusic D., Fazekas J., Foster J. Field-programmable gate arrays (Proceedings of the 2005 ACM/SIGDA 13th International Symposium on Field-programmable Gate Arrays, Monterey, California, Feb 20-22, 2005) 107-117, 2005. Type: Proceedings
This is a very exciting piece of research in the general area of configurable, extensible processors and the software/hardware interface. The authors propose a hybrid architecture, consisting of a parameterized very long instruction wo...
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May 23 2006 |
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LZW-based code compression for VLIW embedded systems
Lin C., Xie Y., Wolf W. Design, automation and test in Europe (Proceedings of the Conference on Design, Automation and Test in Europe, Paris, France, Feb 16-20, 2004) 76-81, 2004. Type: Proceedings
This is a relevant piece of work in the domain of dynamic code compression and decompression in deeply embedded central processing units. The authors identify the code between two branch/jump targets as a potentially good candidate for...
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Mar 3 2006 |
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SEU protected CPU for slow control on space vehicles
Brogna A., Bigongiari F., Bertuccelli F., Errico W., Giovannetti S., Pescari E., Saletti R. Electronic design, test and applications (Proceedings of the Second IEEE International Workshop on Electronic Design, Test and Applications,Jan 28-30, 2004) 4222004. Type: Proceedings
Fault-tolerant processing in aerospace applications is the subject of intense research. The authors very correctly identify such environments as posing great challenges in the correct operation of digital systems that are subjected to ...
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Dec 21 2005 |
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Optimizing instruction TLB energy using software and hardware techniques
Kadayif I., Sivasubramaniam A., Kandemir M., Kandiraju G., Chen G. ACM Transactions on Design Automation of Electronic Systems 10(2): 229-257, 2005. Type: Article
In this paper, the authors target the address translation mechanisms of current, state-of-the-art central processing unit (CPU) microarchitectures. In particular, they identify the instruction translation look-aside buffer (iTLB) as a ...
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Oct 13 2005 |
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A programmable vertex shader with fixed-point SIMD datapath for low power wireless applications
Sohn J., Woo R., Yoo H. Graphics hardware (Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Conference on Graphics Hardware, Grenoble, France, Aug 29-30, 2004) 107-114, 2004. Type: Proceedings
Sohn, Woo, and Yoo propose a programmable, low-power vertex shader for mobile terminals, characterized by programmability, single instruction multiple data (SIMD) (vector) processing, and a multi-threaded programming paradigm and micro...
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Jul 8 2005 |
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Pruning-based, energy-optimal, deterministic I/O device scheduling for hard real-time systems
Swaminathan V., Chakrabarty K. ACM Transactions on Embedded Computing Systems 4(1): 141-167, 2005. Type: Article
Swaminathan and Chakrabarty address the issue of optimal job scheduling in a hard real-time computer system, via the use of a novel, off-line dynamic power management (DPM) scheme for computer system input/output (I/O)....
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Jun 15 2005 |
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