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Lopriore, Lanfranco
Universita della Calabria
Arcavacata di Rende, Italy
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1 - 10 of 11
reviews
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Cache inclusion and processor sampling in multiprocessor simulations
Chame J., Dubois M. ACM SIGMETRICS Performance Evaluation Review 21(1): 36-47, 1993. Type: Article
In a multiprocessor system consisting of a large number of processors, each of which has a private cache memory, critical design problems are the cache architecture and the cache coherence protocols. Trace-driven simulation is a common...
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Aug 1 1994 |
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A guide to RISC microprocessors
Slater M., Academic Press Prof., Inc., San Diego, CA, 1992. Type: Book (9780126491401)
A number of implementations of the reduced instruction set computer (RISC) design philosophy, as embodied by outstanding microprocessor families available commercially, are discussed in this collection of review articles. The ...
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Dec 1 1993 |
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MIPS RISC architectures
Kane G., Heinrich J., Prentice-Hall, Inc., Upper Saddle River, NJ, 1992. Type: Book (9780135904725)
MIPS is an application of the reduced instruction set computer (RISC) concept to the design of a microprocessor architecture. At present, this architecture is embodied by the R-Series (R2000, R3000, R6000, and the new R4000) processors...
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Nov 1 1992 |
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The effects of processor architecture on instruction memory traffic
Mitchell C., Flynn M. ACM Transactions on Computer Systems 8(3): 230-250, 2000. Type: Article
Rather than investigating the effects of different cache parameters, this simulation study on instruction memory traffic in the presence of a cache focuses on processor design issues. As pointed out by the authors, this paper ̶...
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Oct 1 1991 |
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Dynamic Instruction Scheduling and the Astronautics ZS-1
Smith J. Computer 22(7): 21-35, 1989. Type: Article
Smith is a member of the project team for the Astronautics ZS-1. The ZS-1 is a high-speed computer system for scientific applications. It uses two instruction pipelines, one for fixed-point and memory addressing operations, the other f...
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Oct 1 1990 |
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A Taxonomy for Computer Architectures
Skillicorn D. Computer 21(11): 46-57, 1988. Type: Article
This paper presents a new taxonomy for computer architectures that is based on partitioning the architectures into functional units and considering the information flow between these units. This taxonomy forms a two-level structure. At...
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Sep 1 1989 |
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Measurement and evaluation of the MIPS architecture and processor
Gross T., Hennessy J., Przybylski S., Rowen C. ACM Transactions on Computer Systems 6(3): 229-257, 1988. Type: Article
This paper presents the results of a large number of measurements on the performance of MIPS, a 32-bit reduced instruction set computer (RISC) architecture implemented at Stanford University between 1981 and 1984 as a single-chip micro...
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Apr 1 1989 |
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A simulation study of the CRAY X-MP memory system
Cheung T., Smith J. IEEE Transactions on Computers 35(7): 613-622, 1986. Type: Article
The CRAY X-MP is a dual-processor vector supercomputer developed as an evolution of the CRAY-1S. It has a 32-way interleaved memory system which is organized into four sections of eight memory banks. Each processor has four ports, one ...
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Feb 1 1987 |
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Write-once laser disc technology
Slonim J., Mole D. (ed), Bauer M. (ed) Library Hi Tech 3(4): 27-42, 1986. Type: Article
The principles of optical disc technology are presented in this paper, with particular reference to write-once digital discs. The basic categories of recording medium are first compared, the optical disc recording process is then analy...
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Oct 1 1986 |
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Reduced instruction set computer architectures for VLSI
Katevenis M., Massachusetts Institute of Technology, Cambridge, MA, 1985. Type: Book (9789780262111034)
The author is a member of the Reduced Instruction Set Computer (RISC) project team at the University of California at Berkeley. This project was aimed at the design and subsequent implementation of a RISC architecture. As a result, two...
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Feb 1 1986 |
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