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	Rooholamin, Seyed A.     Options: All Media Types Journals Proceedings Div Books Whole Books Other Date Reviewed Title Author Publisher Published Date Descending Ascending Date Reviewed     1 - 1 of 1 reviews       Modular vector processor architecture targeting at data-level parallelism Rooholamin S., Ziavras S. Microprocessors & Microsystems 39(4): 237-249, 2015.  Type: Article This research presents a VHSIC hardware description language (VHDL) vector processor architecture specifically designed to address data-level parallelism by separating the vector lanes to use its own private memory, avoiding any stalls...... Apr 8 2016
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