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	Kalyanaraman, Ravi     Options: All Media Types Journals Proceedings Div Books Whole Books Other Date Reviewed Title Author Publisher Published Date Descending Ascending Date Reviewed     1 - 1 of 1 reviews       Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming Vemuri R., Kalyanaraman R. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3(2): 201-214, 1995.  Type: Article Verification of the correctness of hardware designs is getting more attention thanks to some highly visible design flaws in certain products. As hardware description languages, such as VHDL, are used in design, the problem becomes more...... Jul 1 1996
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