As the authors demonstrate in this paper, observability analysis at the behavioral level, before operations are scheduled, can lead to significant reductions in power consumption. This is done by gating clocks on the output registers of the gated operations. The authors state the problem explored in this paper:

Given a [control/data flow graph (CDFG)] and profiling information, as well as the cost (average power) for executing each instruction, find a schedule that leads to the smallest [power consumption] ... subject to data-dependency constraints and a latency constraint.

To improve computational efficiency, the authors use a heuristic approach with approximations. They compare their method to real-world examples: “our method achieves an average of 33.9 percent reduction in total power; it outperforms a previous method by 17.1 percent on average and gives close-to-optimal solutions on several designs.” In their experiments, they use designs that range from 88 to 1,306 nodes in the CDFG. The designs required a maximum of 60 seconds of computer time, whereas an exact integer linear programming (ILP) algorithm could not find any solution for the larger designs in 7,200 seconds of computer time. Furthermore, it improved on the heuristic results by only 1 percent for the smaller designs.

In order to fully comprehend this paper, readers must have extensive mathematical sophistication and familiarity with scheduling algorithms, ILP algorithms, and compiler design. If you have the appropriate background and are willing to put in the effort, this paper has a lot to offer.