A reconfigurable architecture, based on double-gate (DG) transistor circuits, that could be suitable for implementing low-power reconfigurable logic arrays, targeting future nanoscale technologies, is discussed in this paper. The operation of DG transistors is described, and then an example implementation of a reconfigurable array is presented based on those devices.

In assembling the logic array based on the DG devices, the main goal is to achieve a simple organization that can be configured using the control gates of the complementary transistors. The proposed array is polymorphic, since it might be arbitrarily configured as logic and/or interconnect, or as combinations of both. Moreover, it can be used to implement complex datapath architectures. The synthesis of both combinational and sequential logic is demonstrated. Simulation results have been presented for area, static power, and delay, and comparisons have been made to display the efficacy of the reconfigurable array.

The paper introduces an interesting approach in using DG transistors for the implementation of logic arrays, but there are some concerns: the placement and routing of circuits are not really done, and results have been obtained based on a number of conservative assumptions. On the design-automation side, it would be better to study the amount of engineering effort that should be devoted to modifying the physical design tools for the proposed logic array. In addition, clear estimations of reconfiguration overhead time and reconfiguration bit-stream size have not been reported, while these specifications might be of great importance in implementing applications on logic arrays. Finally, the capability of the proposed array to support partial reconfigurability is not clear.