Verification of the correctness of hardware designs is getting more attention thanks to some highly visible design flaws in certain products. As hardware description languages, such as VHDL, are used in design, the problem becomes more like software verification, but it is easier because of a more constrained design space and fewer lines of code.

This paper reports on a system that generates design verification tests from VHDL code. First, paths through the code are enumerated. Then, constraints for variables in each path are generated. Constraints can be generated for both the single- and the multiple-process cases. Finally, a constraint solver is used to generate the verification tests.

Fault simulation is used to validate the effectiveness of the tests. When one test per path is generated, fault coverage is relatively low, except for control-dominated designs. When more than one test per path is generated (up to 500), fault coverage increases to the 90s.

The procedure seems plausible, and the results are good. The limitation of any path enumeration method, namely the large number of potential paths, is addressed well. Unfortunately, due to the lack of any metric of design verification coverage better than stuck-at fault coverage, the true effectiveness of this technique in discovering design errors is not known.