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A MapReduce scratchpad memory for multi-core cloud computing applications
Kachris C., Sirakoulis G., Soudris D. Microprocessors & Microsystems39 (8):599-608,2015.Type:Article
Date Reviewed: May 19 2016

MapReduce is a programming framework that is widely used for data center cloud computing or multicore system-on-chip (SoC) applications. The goal is to process and generate large datasets. MapReduce is a two-step function: the first step, called Map function, is to process a key/value pair to generate a set of intermediate pairs, and the second step is the Reduce function that merges these intermediate values associated with the same intermediate key. The challenges of implementing the MapReduce function in hardware is the performance bottleneck (memory access time) because several resources need to be allocated from node processors, and the key/value pairs organized in memory structures can waste a lot of central processing unit (CPU) cycles.

In this paper, Kachris et al. propose a novel solution to accelerate the MapReduce framework by incorporating a special local scratchpad memory to multicore systems to reduce the memory access time of the key/value pairs and accelerate the processing of these values. The scratchpad memory is not a new concept and has been used in application-specific processors, like graphic processors; rather, the contribution of this paper is the introduction of scratchpad memory in the cloud computing domain and its use as a special co-processor for MapReduce applications. The key idea is to keep all key/value pairs in this dedicated memory that is much closer to the processors compared to cache and main memory. This paper presents the programming change and memory architecture difference for using the scratchpad memory.

To evaluate the performance of the proposed solution, the authors implement the scheme on a field-programmable gate array (FPGA)-based SoC (Xilinx Zynq) with hard-core processors as the prototyping. The results show the significant reduction of the execution time (maximum speedup is 2.3X) by running several benchmarks with various dataset sizes. The area overhead of the scheme is very small. In terms of the power consumption, the proposed solution can also reduce the total energy consumption from 1.2X to 2.3X depending on the specific applications. Overall, the scratch memory solution can reduce both the execution time and energy consumption of the processors. It can also be adapted to other applications by minor modifications.

This work is a good example of exploring opportunities by adapting the existing infrastructures to new challenges. Also, it fits well with the notion of a customized computing trend, in which dedicated accelerators are employed for different applications or algorithms (for example, MapReduce, as shown in this work). The work is well evaluated, with both simulation and emulation on actual FPGA hardware. The results are promising because usually it is very hard to achieve both energy reduction and performance improvements; this proposed scheme provides both improvements while keeping the overhead minimal. The extension of the work can be to apply the idea to wider applications and to make it reconfigurable based on the workload.

Reviewer:  Xinfei Guo Review #: CR144425 (1609-0655)
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Multiple Data Stream Architectures (Multiprocessors) (C.1.2 )
 
 
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